The designers of chips connect cores or Intellectual Property (IP) blocks, which comprise logic cells and often multiple ports. Certain software, for chip design, displays chip floorplans. Floorplans define various physical regions, in which the logic cells of certain cores or IPs can be placed and blockages where no logic cells can be placed.
A network-on-chip (NoC) is an efficient and widely used mechanism for connecting cores and IP blocks in a System-on-Chip (SoC). Cores have standard interfaces or ports. A SoC connects cores through their interfaces, in order for the cores or IPs to communicate with each other. A SoC includes logic cells, which are placed throughout the floorplan, and wires, which are routed throughout the floorplan. A SoC includes an array of IP blocks that are implemented as either “hard” blocks, whose physical shape and size is mostly fixed, or “soft” blocks, which are generally implemented at the end of a design cycle, using space left by the hard blocks. For example, an interconnect of a SoC connects communication ports on both hard and soft IPs with “links”. The interconnect is an IP that is a soft IP.
Developing a physical interconnect topology can be done using conventional approaches for SoCs or chips with small numbers of IP blocks and simple floorplans. However, chips now include many cores or IPs and the number is growing increasingly larger with correspondingly more complex floorplans. Given a SoC with a highly irregular floorplan and more than 100 IP port connections, it is very challenging to generate an interconnect topology that is near-optimal for the floorplan and various QoR metrics, such metrics including, for example, area, power, frequency performance, bandwidth, etc. Therefore, what is needed is a method and a system to synthesize the design of a complex or irregular SoC interconnect network topology within the physical implementation and constraints of a floorplan.